Processor pipelining is a known technique used to make microprocessors operate more quickly. This technique enables a microprocessor to work on different steps of an instruction at the same time and thereby take advantage of parallelism that exists among the steps needed to execute an instruction. As a result, a microprocessor can execute more instructions in a shorter period of time.
Many microprocessors, especially those used in the embedded market, are relatively simple in-order machines. As a result, they are subject to data hazard stalls. More complex microprocessors have out-of-order pipelines, which allow execution of instructions to be scheduled around hazards that would stall an in-order processor pipeline.
Speculation is used to resolve branch instructions and predict whether a conditional branch is taken or not taken in an out-of-order machine. When a branch resolution results in a misprediction, all younger instructions in a program stream must be cleared from the pipeline. Conventionally, this is accomplished using an age-based comparison technique across the entire processor pipeline. While this conventional technique works for its intended purpose, it requires maintaining and updating a number of register renaming maps, especially in microprocessors that employ a pipeline having a large number of processing stages.
What is needed is a new technique for clearing an out-of-order pipeline of a microprocessor following a branch misprediction, which overcomes the deficiencies noted above.